The present invention relates to a semiconductor memory device including a latch circuit for storing complementary data at two storage nodes.
There has been known a latch circuit in which an output of a first inverter is connected to an input of a second inverter and an output of the second inverter is connected to an input of the first inverter. Each of respective output nodes of the inverters forms a storage node. When each of the inverters has a CMOS structure, a CMOS latch circuit is obtained.
An SRAM memory cell having a 6-transistor structure utilizes the CMOS latch circuit and includes two load transistors, two drive transistors and two access transistors.
According to the techniques disclosed in U.S. Pat. No. 6,316,812 and Japanese Laid-Open Publication No. 2002-42476, to expand a power supply voltage range in which an SRAM memory cell can be operated, a voltage drop element is inserted between a supply line of a power supply voltage and each of respective sources of two load transistors. In writing data into a memory cell, source voltages of the load transistors are reduced, thereby making it easier to reverse a voltage at a storage node held at a high logic level (“H” level) to a low logic level (“L” level).
According to the technique disclosed in United States Patent Application Publication No. 2003/0223276, a threshold voltage of a transistor in an SRAM memory cell is detected. Then, according to the threshold voltage, a power supply voltage of the memory cell is compared to a power supply voltage of a peripheral circuit and is adjusted to an optimal voltage. Furthermore, a substrate bias is adjusted.